The design very high speed and high precision integrated circuits involves many design choices and trade-offs. One of the most difficult tasks in integrated circuit design is timing closure. Achieving timing closure means that all the parts of the integrated circuit generate their outputs in time for proper operation of the next circuit. The rise time on a signal line varies directly with the drive capacity of the driving circuit. The drive capacity typically varies directly with the channel width of the driving transistors. This rise time varies inversely with the capacitance driven. The driven capacitance includes the gate capacitance of the inputs of the driven circuits and the wire capacitance of all wires of the signal line.
Most of these quantities are under control of the integrated circuit designer or can be easily estimated. The driving circuit channel width and thus the drive strength are directly specified by the integrated circuit design. Likewise the driven gate capacitance is controlled by the design selected. The designer has direct control over the fan-out. Fan-out is the number of inputs driven by that signal line. The respective gate capacitances of the driven inputs correspond to the particular circuit selected for each input device. Thus this factor is easily estimated. The wire capacitance is not so easily estimated. The wire capacitance depends primarily upon the length of the signal line. This signal line capacitance can also be estimated. However, the wire capacitance generally includes a considerable proportion of parasitic capacitance. Parasitic capacitance consists of capacitance between the signal line and other structures not normally considered in estimating capacitance. These other structures include other signal lines on the same metal layer, lines on other metal layers and other structures that contribute to capacitance. Parasitic capacitance varies widely and can be particularly difficult to estimate in current designs with multi-level metal and large numbers of crowded structures.
There are a number of commercial parasitic calculation tools available to the integrated circuit designer. The integrated circuit designer is faced with two choices in using these tools. First, the designer can use the parasitic capacitance calculation tool to accurately calculate the parasitic capacitance of each network node in the circuit. This selection typically requires a large amount of computation and is thus typically very slow. Second, the designed can use the parasitic capacitance calculation tool using a lower accuracy. This selection will yield answers in a timely manner. However, there is no guarantee that these parasitic capacitance calculations will correctly predict the actual circuit behavior.